This application relates to co-pending U.S. patent application Ser. No. 09/398,872, filed on even date herewith, entitled A Method for a Dynamic Termination Logic Driver with Improved Slew Rate Control and naming Michael A. Ang, Alexander D. Taylor, Jonathan E. Starr, and Sai V. Vishwanthaiah as inventors, the application being incorporated herein by reference in its entirety.
This application relates to co-pending U.S. patent application Ser. No. 09/399,453, filed on even date herewith, entitled A Dynamic Termination Logic Driver with Improved Slew Rate Control and naming Michael A. Ang, Alexander D. Taylor, Jonathan E. Starr, and Sai V. Vishwanthaiah as inventors, the application being incorporated herein by reference in its entirety.
This application relates to co-pending U.S. patent application Ser. No. 09/326,964, filed on Jun. 7, 1999, entitled Output Driver With Improved Impedance Control and naming Michael A. Ang, Alexander D. Taylor, Jonathan E. Starr, and Sai V. Vishwanthaiah as inventors, the application being incorporated herein by reference in its entirety.
This application relates to co-pending U.S. patent application Ser. No. 09/327,220, filed on Jun. 7, 1999, entitled Method For An Output Driver With Improved Impedance Control and naming Michael A. Ang, Alexander D. Taylor, Jonathan E. Starr, and Sai V. Vishwanthaiah as inventors, the application being incorporated herein by reference in its entirety.
This application relates to co-pending U.S. patent application Ser. No. 09/326,909, filed on Jun. 7, 1999, entitled Output Driver With Improved Slew Rate Control and naming Michael A. Ang, Alexander D. Taylor, Jonathan E. Starr, and Sai V. Vishwanthaiah as inventors, the application being incorporated herein by reference in its entirety.
This application relates to co-pending U.S. patent application Ser. No. 09/327,057, filed on Jun. 7, 1999, entitled Method For An Output Driver With Improved Slew Rate Control and naming Michael A. Ang, Alexander D. Taylor, Jonathan E. Starr, and Sai V. Vishwanthaiah as inventors, the application being incorporated herein by reference in its entirety.
1. Field of the Invention
The present invention relates to driver circuits and more particularly to driver circuits for use in information processing systems.
2. Description of the Related Art
In computer and information processing systems, various integrated circuit chips must communicate digitally with each other over common buses. The signal frequency at which this communication occurs can limit the performance of the overall system. Thus, the higher the communication frequency, the better. The maximum frequency at which a system communicates is a function not only of the time that it takes for the electromagnetic wavefronts to propagate on the bus from one chip to another, but also of the time required for the signals to settle to levels that can be reliably recognized at the receiving bus nodes as being HIGH or LOW, referred to as the settling time.
There are several factors which affect the settling time of a signal. For example, the "slew rate" of the launched signal, i.e., the rate at which the voltage level of the launched signal changes from one level to another, is one factor which affects the settling time of the signal. The oscillations in the voltage level of the signal (i.e., the "ringing") due to the effects of package inductance, pad capacitance and other "parasitics" is another factor which affects the settling time of the signal. Ringing due to reflections from impedance mismatches within the bus system is another factor which affects the settling time of the signal. The voltage level of the launched signal relative to the overall signal swing (i.e., the difference between high and low voltage levels of the signal) is another factor which affects the settling time of the signal. The effectiveness of the termination of the bus is another factor which affects the settling time of the signal.
The operating characteristics of transistors such as CMOS transistors, from which drivers are typically constructed, change under a variety of conditions, often referred to as process, voltage, temperature (PVT) variations. PVT variations may be conceptualized as a box across which the operating characteristics of the transistors move. One of ordinary skill in the art will appreciate that the three characteristics, process, voltage and temperature can be visualized as a three dimensional graph with a "slow corner" identifying a point when the three characteristics affect operating conditions, and a "fast corner" identifying a point when the three characteristics do not greatly affect operating conditions. For example, the operating characteristics may move from a fastest corner of PVT variations to a slowest corner of PVT variations, and everywhere in between. More specifically, the operating characteristics due to PVT variations may change with variations in manufacturing process as well as with variations in operating conditions such as junction temperature and supply voltage levels. The operating characteristics may also change with variations of voltage differences across the transistor terminals of the driver; the voltage differences may change as the voltage level at the output node of the driver changes.
If inadequate compensation is made for these variations, the output slew rate and output impedance of the driver may vary substantially within a particular driver as well as from driver to driver on a chip.
Another characteristic that is desirable to control within a driver is crowbar current. The crowbar current is the current that flows directly between the supply rails of a driver through the pull up and pull down units of a driver if both units are enabled simultaneously. Having high crowbar current may cause the driver to consume more power than necessary to provide adequate driver performance.
It is known to provide drivers having different termination characteristics. For example, a High Speed Transceiver Logic (HSTL) type driver, may be designed to terminate at the driver end of a transmission line; a Dynamic Termination Logic (DTL) type driver may be designed to terminate at the receiver end of a transmission line. Each of these driver types has characteristics that affect the driver when a particular type is chosen for a design. What is needed is a driver that provides adequate performance under the different characteristics that affect the driver design.